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https://github.com/stenzek/duckstation.git
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CPU/Recompiler: Don't back up value to stack in mtc0
Fixes misaligned stack that could crash in log messages.
This commit is contained in:
parent
568667753d
commit
fe1fa765f7
@ -31,10 +31,6 @@ LOG_CHANNEL(Recompiler);
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#define PTR(x) vixl::aarch32::MemOperand(RSTATE, (((u8*)(x)) - ((u8*)&g_state)))
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#define PTR(x) vixl::aarch32::MemOperand(RSTATE, (((u8*)(x)) - ((u8*)&g_state)))
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#define RMEMBASE vixl::aarch32::r3
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#define RMEMBASE vixl::aarch32::r3
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static constexpr u32 FUNCTION_CALLEE_SAVED_SPACE_RESERVE = 80; // 8 registers
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static constexpr u32 FUNCTION_CALLER_SAVED_SPACE_RESERVE = 144; // 18 registers -> 224 bytes
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static constexpr u32 FUNCTION_STACK_SIZE = FUNCTION_CALLEE_SAVED_SPACE_RESERVE + FUNCTION_CALLER_SAVED_SPACE_RESERVE;
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#define RRET vixl::aarch32::r0
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#define RRET vixl::aarch32::r0
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#define RRETHI vixl::aarch32::r1
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#define RRETHI vixl::aarch32::r1
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#define RARG1 vixl::aarch32::r0
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#define RARG1 vixl::aarch32::r0
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@ -266,9 +262,6 @@ u32 CPU::CodeCache::EmitASMFunctions(void* code, u32 code_size)
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g_enter_recompiler = armAsm->GetCursorAddress<decltype(g_enter_recompiler)>();
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g_enter_recompiler = armAsm->GetCursorAddress<decltype(g_enter_recompiler)>();
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{
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{
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// reserve some space for saving caller-saved registers
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armAsm->sub(sp, sp, FUNCTION_STACK_SIZE);
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// Need the CPU state for basically everything :-)
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// Need the CPU state for basically everything :-)
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armMoveAddressToReg(armAsm, RSTATE, &g_state);
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armMoveAddressToReg(armAsm, RSTATE, &g_state);
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}
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}
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@ -2273,9 +2266,8 @@ void CPU::ARM32Recompiler::Compile_mtc0(CompileFlags cf)
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Flush(FLUSH_FOR_C_CALL);
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Flush(FLUSH_FOR_C_CALL);
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SwitchToFarCodeIfBitSet(changed_bits, 16);
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SwitchToFarCodeIfBitSet(changed_bits, 16);
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armAsm->push(RegisterList(RARG1));
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EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
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EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
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armAsm->pop(RegisterList(RARG1));
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armAsm->ldr(RARG1, PTR(ptr)); // reload value for interrupt test below
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if (CodeCache::IsUsingFastmem() && m_block->HasFlag(CodeCache::BlockFlags::ContainsLoadStoreInstructions) &&
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if (CodeCache::IsUsingFastmem() && m_block->HasFlag(CodeCache::BlockFlags::ContainsLoadStoreInstructions) &&
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IsHostRegAllocated(RMEMBASE.GetCode()))
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IsHostRegAllocated(RMEMBASE.GetCode()))
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{
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{
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@ -28,10 +28,6 @@ LOG_CHANNEL(Recompiler);
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#define PTR(x) vixl::aarch64::MemOperand(RSTATE, (((u8*)(x)) - ((u8*)&g_state)))
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#define PTR(x) vixl::aarch64::MemOperand(RSTATE, (((u8*)(x)) - ((u8*)&g_state)))
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static constexpr u64 FUNCTION_CALLEE_SAVED_SPACE_RESERVE = 80; // 8 registers
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static constexpr u64 FUNCTION_CALLER_SAVED_SPACE_RESERVE = 144; // 18 registers -> 224 bytes
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static constexpr u64 FUNCTION_STACK_SIZE = FUNCTION_CALLEE_SAVED_SPACE_RESERVE + FUNCTION_CALLER_SAVED_SPACE_RESERVE;
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#define RWRET vixl::aarch64::w0
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#define RWRET vixl::aarch64::w0
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#define RXRET vixl::aarch64::x0
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#define RXRET vixl::aarch64::x0
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#define RWARG1 vixl::aarch64::w0
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#define RWARG1 vixl::aarch64::w0
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@ -448,9 +444,6 @@ u32 CPU::CodeCache::EmitASMFunctions(void* code, u32 code_size)
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g_enter_recompiler = armAsm->GetCursorAddress<decltype(g_enter_recompiler)>();
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g_enter_recompiler = armAsm->GetCursorAddress<decltype(g_enter_recompiler)>();
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{
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{
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// reserve some space for saving caller-saved registers
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armAsm->sub(sp, sp, FUNCTION_STACK_SIZE);
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// Need the CPU state for basically everything :-)
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// Need the CPU state for basically everything :-)
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armMoveAddressToReg(armAsm, RSTATE, &g_state);
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armMoveAddressToReg(armAsm, RSTATE, &g_state);
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@ -2436,11 +2429,8 @@ void CPU::ARM64Recompiler::Compile_mtc0(CompileFlags cf)
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Flush(FLUSH_FOR_C_CALL);
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Flush(FLUSH_FOR_C_CALL);
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SwitchToFarCodeIfBitSet(changed_bits, 16);
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SwitchToFarCodeIfBitSet(changed_bits, 16);
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armAsm->sub(sp, sp, 16);
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armAsm->str(RWARG1, MemOperand(sp));
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EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
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EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
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armAsm->ldr(RWARG1, MemOperand(sp));
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armAsm->ldr(RWARG1, PTR(ptr)); // reload value for interrupt test below
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armAsm->add(sp, sp, 16);
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armAsm->ldr(RMEMBASE, PTR(&g_state.fastmem_base));
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armAsm->ldr(RMEMBASE, PTR(&g_state.fastmem_base));
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SwitchToNearCode(true);
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SwitchToNearCode(true);
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@ -2286,11 +2286,8 @@ void CPU::RISCV64Recompiler::Compile_mtc0(CompileFlags cf)
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rvAsm->SRLIW(RSCRATCH, changed_bits, 16);
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rvAsm->SRLIW(RSCRATCH, changed_bits, 16);
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rvAsm->ANDI(RSCRATCH, RSCRATCH, 1);
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rvAsm->ANDI(RSCRATCH, RSCRATCH, 1);
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SwitchToFarCode(true, &Assembler::BEQ, RSCRATCH, zero);
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SwitchToFarCode(true, &Assembler::BEQ, RSCRATCH, zero);
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rvAsm->ADDI(sp, sp, -16);
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rvAsm->SW(RARG1, 0, sp);
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EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
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EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
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rvAsm->LW(RARG1, 0, sp);
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rvAsm->LW(new_value, PTR(ptr));
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rvAsm->ADDI(sp, sp, 16);
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rvAsm->LD(RMEMBASE, PTR(&g_state.fastmem_base));
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rvAsm->LD(RMEMBASE, PTR(&g_state.fastmem_base));
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SwitchToNearCode(true);
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SwitchToNearCode(true);
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@ -2243,11 +2243,8 @@ void CPU::X64Recompiler::Compile_mtc0(CompileFlags cf)
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cg->test(changed_bits, 1u << 16);
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cg->test(changed_bits, 1u << 16);
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SwitchToFarCode(true, &CodeGenerator::jnz);
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SwitchToFarCode(true, &CodeGenerator::jnz);
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cg->mov(cg->dword[cg->rsp], RWARG2);
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cg->sub(cg->rsp, STACK_SHADOW_SIZE + 8);
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cg->call(&CPU::UpdateMemoryPointers);
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cg->call(&CPU::UpdateMemoryPointers);
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cg->add(cg->rsp, STACK_SHADOW_SIZE + 8);
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cg->mov(RWARG2, cg->dword[PTR(ptr)]); // reload value for interrupt test below
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cg->mov(RWARG2, cg->dword[cg->rsp]);
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cg->mov(RMEMBASE, cg->qword[PTR(&g_state.fastmem_base)]);
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cg->mov(RMEMBASE, cg->qword[PTR(&g_state.fastmem_base)]);
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SwitchToNearCode(true);
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SwitchToNearCode(true);
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@ -2475,7 +2472,7 @@ u32 CPU::Recompiler::CompileLoadStoreThunk(void* thunk_code, u32 thunk_space, vo
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num_gprs++;
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num_gprs++;
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}
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}
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const u32 stack_size = (((num_gprs + 1) & ~1u) * GPR_SIZE) + STACK_SHADOW_SIZE;
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const u32 stack_size = (((num_gprs + 1) & ~1u) * GPR_SIZE);
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if (stack_size > 0)
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if (stack_size > 0)
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{
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{
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