mirror of
https://github.com/stenzek/duckstation.git
synced 2025-06-07 20:15:32 +00:00
8a1b4d8bee
Plenty of games seem to suffer from this issue where they have a linked list DMA going while polling the controller. Having a large slice size causes the serial transfer to complete before the silly busy wait in the BIOS poll routine returns, resulting in it thinking that the controller is disconnected. Some games are very sensitive to this (e.g. Newman Haas Racing), to the point that even using a slice size of 1 is insufficient for avoiding the race, probably due to the linked list layout. Therefore, without major refactoring to ensure the CPU runs every DMA block, and the associated performance penalty, we just halt the DMA until the serial transfers have completed. To reduce the chances of this significantly affecting timing, we add accumulate the ticks that have been "lost", and allow them to be "used up" when the transfer does happen.
1033 lines
34 KiB
C++
1033 lines
34 KiB
C++
// SPDX-FileCopyrightText: 2019-2024 Connor McLaughlin <stenzek@gmail.com>
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// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
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#include "dma.h"
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#include "bus.h"
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#include "cdrom.h"
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#include "cpu_code_cache.h"
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#include "cpu_core.h"
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#include "gpu.h"
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#include "host.h"
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#include "imgui.h"
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#include "interrupt_controller.h"
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#include "mdec.h"
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#include "pad.h"
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#include "spu.h"
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#include "system.h"
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#include "util/imgui_manager.h"
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#include "util/state_wrapper.h"
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#include "common/bitfield.h"
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#include "common/log.h"
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#include "common/string_util.h"
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#include "fmt/format.h"
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#include <array>
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#include <memory>
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#include <vector>
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Log_SetChannel(DMA);
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namespace DMA {
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namespace {
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enum class SyncMode : u32
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{
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Manual = 0,
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Request = 1,
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LinkedList = 2,
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Reserved = 3
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};
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static constexpr PhysicalMemoryAddress BASE_ADDRESS_MASK = UINT32_C(0x00FFFFFF);
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static constexpr PhysicalMemoryAddress TRANSFER_ADDRESS_MASK = UINT32_C(0x00FFFFFC);
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static constexpr PhysicalMemoryAddress LINKED_LIST_TERMINATOR = UINT32_C(0x00FFFFFF);
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static constexpr TickCount LINKED_LIST_HEADER_READ_TICKS = 10;
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static constexpr TickCount LINKED_LIST_BLOCK_SETUP_TICKS = 5;
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static constexpr TickCount HALT_TICKS_WHEN_TRANSMITTING_PAD = 100;
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struct ChannelState
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{
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u32 base_address = 0;
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union BlockControl
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{
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u32 bits;
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union
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{
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BitField<u32, u32, 0, 16> word_count;
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u32 GetWordCount() const { return (word_count == 0) ? 0x10000 : word_count; }
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} manual;
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union
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{
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BitField<u32, u32, 0, 16> block_size;
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BitField<u32, u32, 16, 16> block_count;
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u32 GetBlockSize() const { return (block_size == 0) ? 0x10000 : block_size; }
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u32 GetBlockCount() const { return (block_count == 0) ? 0x10000 : block_count; }
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} request;
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} block_control = {};
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union ChannelControl
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{
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u32 bits;
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BitField<u32, bool, 0, 1> copy_to_device;
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BitField<u32, bool, 1, 1> address_step_reverse;
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BitField<u32, bool, 8, 1> chopping_enable;
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BitField<u32, SyncMode, 9, 2> sync_mode;
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BitField<u32, u32, 16, 3> chopping_dma_window_size;
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BitField<u32, u32, 20, 3> chopping_cpu_window_size;
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BitField<u32, bool, 24, 1> enable_busy;
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BitField<u32, bool, 28, 1> start_trigger;
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static constexpr u32 WRITE_MASK = 0b01110001'01110111'00000111'00000011;
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} channel_control = {};
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bool request = false;
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};
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union DPCR
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{
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u32 bits;
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BitField<u32, u8, 0, 3> MDECin_priority;
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BitField<u32, bool, 3, 1> MDECin_master_enable;
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BitField<u32, u8, 4, 3> MDECout_priority;
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BitField<u32, bool, 7, 1> MDECout_master_enable;
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BitField<u32, u8, 8, 3> GPU_priority;
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BitField<u32, bool, 10, 1> GPU_master_enable;
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BitField<u32, u8, 12, 3> CDROM_priority;
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BitField<u32, bool, 15, 1> CDROM_master_enable;
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BitField<u32, u8, 16, 3> SPU_priority;
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BitField<u32, bool, 19, 1> SPU_master_enable;
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BitField<u32, u8, 20, 3> PIO_priority;
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BitField<u32, bool, 23, 1> PIO_master_enable;
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BitField<u32, u8, 24, 3> OTC_priority;
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BitField<u32, bool, 27, 1> OTC_master_enable;
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BitField<u32, u8, 28, 3> priority_offset;
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BitField<u32, bool, 31, 1> unused;
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ALWAYS_INLINE u8 GetPriority(Channel channel) const { return ((bits >> (static_cast<u8>(channel) * 4)) & u32(3)); }
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ALWAYS_INLINE bool GetMasterEnable(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) * 4 + 3)) & u32(1));
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}
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};
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static constexpr u32 DICR_WRITE_MASK = 0b00000000'11111111'10000000'00111111;
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static constexpr u32 DICR_RESET_MASK = 0b01111111'00000000'00000000'00000000;
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union DICR
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{
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u32 bits;
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BitField<u32, bool, 15, 1> bus_error;
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BitField<u32, bool, 16, 1> MDECin_irq_enable;
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BitField<u32, bool, 17, 1> MDECout_irq_enable;
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BitField<u32, bool, 18, 1> GPU_irq_enable;
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BitField<u32, bool, 19, 1> CDROM_irq_enable;
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BitField<u32, bool, 20, 1> SPU_irq_enable;
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BitField<u32, bool, 21, 1> PIO_irq_enable;
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BitField<u32, bool, 22, 1> OTC_irq_enable;
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BitField<u32, bool, 23, 1> master_enable;
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BitField<u32, bool, 24, 1> MDECin_irq_flag;
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BitField<u32, bool, 25, 1> MDECout_irq_flag;
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BitField<u32, bool, 26, 1> GPU_irq_flag;
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BitField<u32, bool, 27, 1> CDROM_irq_flag;
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BitField<u32, bool, 28, 1> SPU_irq_flag;
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BitField<u32, bool, 29, 1> PIO_irq_flag;
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BitField<u32, bool, 30, 1> OTC_irq_flag;
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BitField<u32, bool, 31, 1> master_flag;
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ALWAYS_INLINE bool GetIRQEnabled(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 16)) & 1u);
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}
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ALWAYS_INLINE bool GetIRQFlag(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 24)) & 1u);
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}
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ALWAYS_INLINE void SetIRQFlag(Channel channel) { bits |= (1u << (static_cast<u8>(channel) + 24)); }
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ALWAYS_INLINE bool ShouldSetIRQFlag(Channel channel)
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{
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// bus errors trigger IRQ unconditionally, completion requires the master flag to be enabled
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return ConvertToBoolUnchecked(((bits >> (static_cast<u8>(channel) + 16)) & ((bits >> 23) & 1u)));
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}
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ALWAYS_INLINE void UpdateMasterFlag()
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{
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master_flag =
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(((bits & (1u << 15)) != 0u) || // bus error, or
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(((bits & (1u << 23)) != 0u) != 0u && (bits & (0b1111111u << 24)) != 0u)); // master enable + irq on any channel
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}
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};
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} // namespace
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static void ClearState();
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// is everything enabled for a channel to operate?
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static bool CanTransferChannel(Channel channel, bool ignore_halt);
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static bool IsTransferHalted();
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static void UpdateIRQ();
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static void HaltTransfer(TickCount duration);
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static void UnhaltTransfer(void*, TickCount ticks, TickCount ticks_late);
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template<Channel channel>
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static bool TransferChannel();
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static bool IsLinkedListTerminator(PhysicalMemoryAddress address);
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static bool CheckForBusError(Channel channel, ChannelState& cs, PhysicalMemoryAddress address, u32 size);
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static void CompleteTransfer(Channel channel, ChannelState& cs);
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// from device -> memory
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template<Channel channel>
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static TickCount TransferDeviceToMemory(u32 address, u32 increment, u32 word_count);
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// from memory -> device
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template<Channel channel>
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static TickCount TransferMemoryToDevice(u32 address, u32 increment, u32 word_count);
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// configuration
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static TickCount s_max_slice_ticks = 1000;
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static TickCount s_halt_ticks = 100;
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static std::vector<u32> s_transfer_buffer;
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static std::unique_ptr<TimingEvent> s_unhalt_event;
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static TickCount s_halt_ticks_remaining = 0;
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static std::array<ChannelState, NUM_CHANNELS> s_state;
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static DPCR s_DPCR = {};
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static DICR s_DICR = {};
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static constexpr std::array<bool (*)(), NUM_CHANNELS> s_channel_transfer_functions = {{
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&TransferChannel<Channel::MDECin>,
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&TransferChannel<Channel::MDECout>,
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&TransferChannel<Channel::GPU>,
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&TransferChannel<Channel::CDROM>,
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&TransferChannel<Channel::SPU>,
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&TransferChannel<Channel::PIO>,
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&TransferChannel<Channel::OTC>,
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}};
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[[maybe_unused]] static constexpr std::array<const char*, NUM_CHANNELS> s_channel_names = {
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{"MDECin", "MDECout", "GPU", "CDROM", "SPU", "PIO", "OTC"}};
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}; // namespace DMA
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template<>
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struct fmt::formatter<DMA::Channel> : fmt::formatter<fmt::string_view>
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{
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auto format(DMA::Channel channel, fmt::format_context& ctx) const
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{
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return formatter<fmt::string_view>::format(DMA::s_channel_names[static_cast<u32>(channel)], ctx);
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}
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};
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void DMA::Initialize()
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{
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s_max_slice_ticks = g_settings.dma_max_slice_ticks;
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s_halt_ticks = g_settings.dma_halt_ticks;
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s_unhalt_event =
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TimingEvents::CreateTimingEvent("DMA Transfer Unhalt", 1, s_max_slice_ticks, &DMA::UnhaltTransfer, nullptr, false);
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Reset();
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}
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void DMA::Shutdown()
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{
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ClearState();
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s_unhalt_event.reset();
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}
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void DMA::Reset()
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{
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ClearState();
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s_unhalt_event->Deactivate();
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}
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void DMA::ClearState()
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = s_state[i];
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cs.base_address = 0;
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cs.block_control.bits = 0;
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cs.channel_control.bits = 0;
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cs.request = false;
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}
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s_DPCR.bits = 0x07654321;
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s_DICR.bits = 0;
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s_halt_ticks_remaining = 0;
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}
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bool DMA::DoState(StateWrapper& sw)
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{
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sw.Do(&s_halt_ticks_remaining);
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = s_state[i];
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sw.Do(&cs.base_address);
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sw.Do(&cs.block_control.bits);
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sw.Do(&cs.channel_control.bits);
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sw.Do(&cs.request);
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}
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sw.Do(&s_DPCR.bits);
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sw.Do(&s_DICR.bits);
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if (sw.IsReading())
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{
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if (s_halt_ticks_remaining > 0)
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s_unhalt_event->SetIntervalAndSchedule(s_halt_ticks_remaining);
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else
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s_unhalt_event->Deactivate();
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}
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return !sw.HasError();
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}
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u32 DMA::ReadRegister(u32 offset)
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{
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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{
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Log_TraceFmt("DMA[{}] base address -> 0x{:08X}", static_cast<Channel>(channel_index),
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s_state[channel_index].base_address);
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return s_state[channel_index].base_address;
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}
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case 0x04:
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{
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Log_TraceFmt("DMA[{}] block control -> 0x{:08X}", static_cast<Channel>(channel_index),
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s_state[channel_index].block_control.bits);
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return s_state[channel_index].block_control.bits;
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}
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case 0x08:
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{
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Log_TraceFmt("DMA[{}] channel control -> 0x{:08X}", static_cast<Channel>(channel_index),
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s_state[channel_index].channel_control.bits);
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return s_state[channel_index].channel_control.bits;
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}
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default:
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break;
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}
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}
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else
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{
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if (offset == 0x70)
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{
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Log_TraceFmt("DPCR -> 0x{:08X}", s_DPCR.bits);
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return s_DPCR.bits;
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}
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else if (offset == 0x74)
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{
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Log_TraceFmt("DICR -> 0x{:08X}", s_DICR.bits);
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return s_DICR.bits;
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}
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}
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Log_ErrorFmt("Unhandled register read: {:02X}", offset);
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return UINT32_C(0xFFFFFFFF);
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}
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void DMA::WriteRegister(u32 offset, u32 value)
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{
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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ChannelState& state = s_state[channel_index];
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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{
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state.base_address = value & BASE_ADDRESS_MASK;
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Log_TraceFmt("DMA channel {} base address <- 0x{:08X}", static_cast<Channel>(channel_index),
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state.base_address);
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return;
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}
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case 0x04:
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{
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Log_TraceFmt("DMA channel {} block control <- 0x{:08X}", static_cast<Channel>(channel_index), value);
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state.block_control.bits = value;
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return;
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}
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case 0x08:
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{
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// HACK: Due to running DMA in slices, we can't wait for the current halt time to finish before running the
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// first block of a new channel. This affects games like FF8, where they kick a SPU transfer while a GPU
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// transfer is happening, and the SPU transfer gets delayed until the GPU transfer unhalts and finishes, and
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// breaks the interrupt.
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const bool ignore_halt = !state.channel_control.enable_busy && (value & (1u << 24));
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state.channel_control.bits = (state.channel_control.bits & ~ChannelState::ChannelControl::WRITE_MASK) |
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(value & ChannelState::ChannelControl::WRITE_MASK);
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Log_TraceFmt("DMA channel {} channel control <- 0x{:08X}", static_cast<Channel>(channel_index),
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state.channel_control.bits);
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// start/trigger bit must be enabled for OTC
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if (static_cast<Channel>(channel_index) == Channel::OTC)
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SetRequest(static_cast<Channel>(channel_index), state.channel_control.start_trigger);
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if (CanTransferChannel(static_cast<Channel>(channel_index), ignore_halt))
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{
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if (static_cast<Channel>(channel_index) != Channel::OTC &&
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state.channel_control.sync_mode == SyncMode::Manual && state.channel_control.chopping_enable)
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{
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// Figure out how roughly many CPU cycles it'll take for the transfer to complete, and delay the transfer.
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// Needed for Lagnacure Legend, which sets DICR to enable interrupts after CHCR to kickstart the transfer.
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// This has an artificial 500 cycle cap, setting it too high causes Namco Museum Vol. 4 and a couple of
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// other games to crash... so clearly something is missing here.
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const u32 block_words = (1u << state.channel_control.chopping_dma_window_size);
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const u32 cpu_cycles_per_block = (1u << state.channel_control.chopping_cpu_window_size);
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const u32 blocks = state.block_control.manual.word_count / block_words;
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const TickCount delay_cycles = std::min(static_cast<TickCount>(cpu_cycles_per_block * blocks), 500);
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if (delay_cycles > 1 && true)
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{
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Log_DevFmt("Delaying {} transfer by {} cycles due to chopping", static_cast<Channel>(channel_index),
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delay_cycles);
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HaltTransfer(delay_cycles);
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}
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else
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{
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s_channel_transfer_functions[channel_index]();
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}
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}
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else
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{
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s_channel_transfer_functions[channel_index]();
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}
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}
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return;
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}
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default:
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break;
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}
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}
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else
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{
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switch (offset)
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{
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case 0x70:
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{
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Log_TraceFmt("DPCR <- 0x{:08X}", value);
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s_DPCR.bits = value;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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if (CanTransferChannel(static_cast<Channel>(i), false))
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{
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if (!s_channel_transfer_functions[i]())
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break;
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}
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}
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return;
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}
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case 0x74:
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{
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Log_TraceFmt("DICR <- 0x{:08X}", value);
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s_DICR.bits = (s_DICR.bits & ~DICR_WRITE_MASK) | (value & DICR_WRITE_MASK);
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s_DICR.bits = s_DICR.bits & ~(value & DICR_RESET_MASK);
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UpdateIRQ();
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return;
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}
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default:
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break;
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}
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}
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Log_ErrorFmt("Unhandled register write: {:02X} <- {:08X}", offset, value);
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}
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void DMA::SetRequest(Channel channel, bool request)
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{
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ChannelState& cs = s_state[static_cast<u32>(channel)];
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if (cs.request == request)
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return;
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cs.request = request;
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if (CanTransferChannel(channel, false))
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s_channel_transfer_functions[static_cast<u32>(channel)]();
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}
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void DMA::SetMaxSliceTicks(TickCount ticks)
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{
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s_max_slice_ticks = ticks;
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}
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void DMA::SetHaltTicks(TickCount ticks)
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{
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s_halt_ticks = ticks;
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}
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|
|
ALWAYS_INLINE_RELEASE bool DMA::CanTransferChannel(Channel channel, bool ignore_halt)
|
|
{
|
|
if (!s_DPCR.GetMasterEnable(channel))
|
|
return false;
|
|
|
|
const ChannelState& cs = s_state[static_cast<u32>(channel)];
|
|
if (!cs.channel_control.enable_busy)
|
|
return false;
|
|
|
|
if (cs.channel_control.sync_mode != SyncMode::Manual && (IsTransferHalted() && !ignore_halt))
|
|
return false;
|
|
|
|
return cs.request;
|
|
}
|
|
|
|
bool DMA::IsTransferHalted()
|
|
{
|
|
return s_unhalt_event->IsActive();
|
|
}
|
|
|
|
void DMA::UpdateIRQ()
|
|
{
|
|
[[maybe_unused]] const auto old_dicr = s_DICR;
|
|
s_DICR.UpdateMasterFlag();
|
|
if (!old_dicr.master_flag && s_DICR.master_flag)
|
|
Log_TracePrintf("Firing DMA master interrupt");
|
|
InterruptController::SetLineState(InterruptController::IRQ::DMA, s_DICR.master_flag);
|
|
}
|
|
|
|
ALWAYS_INLINE_RELEASE bool DMA::IsLinkedListTerminator(PhysicalMemoryAddress address)
|
|
{
|
|
return ((address & LINKED_LIST_TERMINATOR) == LINKED_LIST_TERMINATOR);
|
|
}
|
|
|
|
ALWAYS_INLINE_RELEASE bool DMA::CheckForBusError(Channel channel, ChannelState& cs, PhysicalMemoryAddress address,
|
|
u32 size)
|
|
{
|
|
// Relying on a transfer partially happening at the end of RAM, then hitting a bus error would be pretty silly.
|
|
if ((address + size) > Bus::RAM_8MB_SIZE) [[unlikely]]
|
|
{
|
|
Log_DebugFmt("DMA bus error on channel {} at address 0x{:08X} size {}", channel, address, size);
|
|
cs.channel_control.enable_busy = false;
|
|
s_DICR.bus_error = true;
|
|
s_DICR.SetIRQFlag(channel);
|
|
UpdateIRQ();
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
ALWAYS_INLINE_RELEASE void DMA::CompleteTransfer(Channel channel, ChannelState& cs)
|
|
{
|
|
// start/busy bit is cleared on end of transfer
|
|
Log_DebugFmt("DMA transfer for channel {} complete", channel);
|
|
cs.channel_control.enable_busy = false;
|
|
if (s_DICR.ShouldSetIRQFlag(channel))
|
|
{
|
|
Log_DebugFmt("Setting DMA interrupt for channel {}", channel);
|
|
s_DICR.SetIRQFlag(channel);
|
|
UpdateIRQ();
|
|
}
|
|
}
|
|
|
|
template<DMA::Channel channel>
|
|
bool DMA::TransferChannel()
|
|
{
|
|
ChannelState& cs = s_state[static_cast<u32>(channel)];
|
|
|
|
const bool copy_to_device = cs.channel_control.copy_to_device;
|
|
|
|
// start/trigger bit is cleared on beginning of transfer
|
|
cs.channel_control.start_trigger = false;
|
|
|
|
PhysicalMemoryAddress current_address = cs.base_address;
|
|
const PhysicalMemoryAddress increment = cs.channel_control.address_step_reverse ? static_cast<u32>(-4) : UINT32_C(4);
|
|
switch (cs.channel_control.sync_mode)
|
|
{
|
|
case SyncMode::Manual:
|
|
{
|
|
const u32 word_count = cs.block_control.manual.GetWordCount();
|
|
Log_DebugFmt("DMA[{}]: Copying {} words {} 0x{:08X}", channel, word_count, copy_to_device ? "from" : "to",
|
|
current_address);
|
|
|
|
const PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
|
|
if (CheckForBusError(channel, cs, transfer_addr, word_count * sizeof(u32))) [[unlikely]]
|
|
return true;
|
|
|
|
TickCount used_ticks;
|
|
if (copy_to_device)
|
|
used_ticks = TransferMemoryToDevice<channel>(transfer_addr, increment, word_count);
|
|
else
|
|
used_ticks = TransferDeviceToMemory<channel>(transfer_addr, increment, word_count);
|
|
|
|
CPU::AddPendingTicks(used_ticks);
|
|
CompleteTransfer(channel, cs);
|
|
return true;
|
|
}
|
|
|
|
case SyncMode::LinkedList:
|
|
{
|
|
if (!copy_to_device)
|
|
{
|
|
Panic("Linked list not implemented for DMA reads");
|
|
return true;
|
|
}
|
|
|
|
if constexpr (channel == Channel::GPU)
|
|
{
|
|
// Plenty of games seem to suffer from this issue where they have a linked list DMA going while polling the
|
|
// controller. Having a large slice size causes the serial transfer to complete before the silly busy wait
|
|
// in the BIOS poll routine returns, resulting in it thinking that the controller is disconnected. Some games
|
|
// are very sensitive to this (e.g. Newman Haas Racing), to the point that even using a slice size of 1 is
|
|
// insufficient for avoiding the race, probably due to the linked list layout.
|
|
//
|
|
// Therefore, without major refactoring to ensure the CPU runs every DMA block, and the associated performance
|
|
// penalty, we just halt the DMA until the serial transfers have completed. To reduce the chances of this
|
|
// significantly affecting timing, we add accumulate the ticks that have been "lost", and allow them to be
|
|
// "used up" when the transfer does happen.
|
|
//
|
|
if (Pad::IsTransmitting())
|
|
{
|
|
Log_DebugFmt("DMA transfer while transmitting pad - {} ticks are buffered", -s_halt_ticks_remaining);
|
|
if (!s_unhalt_event->IsActive())
|
|
s_unhalt_event->SetIntervalAndSchedule(HALT_TICKS_WHEN_TRANSMITTING_PAD);
|
|
return false;
|
|
}
|
|
}
|
|
|
|
Log_DebugFmt("DMA[{}]: Copying linked list starting at 0x{:08X} to device", channel, current_address);
|
|
|
|
// Prove to the compiler that nothing's going to modify these.
|
|
const u8* const ram_ptr = Bus::g_ram;
|
|
const u32 mask = Bus::g_ram_mask;
|
|
|
|
const TickCount slice_ticks = s_max_slice_ticks + -s_halt_ticks_remaining;
|
|
TickCount remaining_ticks = slice_ticks;
|
|
while (cs.request && remaining_ticks > 0)
|
|
{
|
|
u32 header;
|
|
PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
|
|
if (CheckForBusError(channel, cs, current_address, sizeof(header))) [[unlikely]]
|
|
{
|
|
cs.base_address = current_address;
|
|
return true;
|
|
}
|
|
|
|
std::memcpy(&header, &ram_ptr[transfer_addr & mask], sizeof(header));
|
|
const u32 word_count = header >> 24;
|
|
const u32 next_address = header & 0x00FFFFFFu;
|
|
Log_TraceFmt(" .. linked list entry at 0x{:08X} size={}({} words) next=0x{:08X}", current_address,
|
|
word_count * 4, word_count, next_address);
|
|
|
|
const TickCount setup_ticks = (word_count > 0) ?
|
|
(LINKED_LIST_HEADER_READ_TICKS + LINKED_LIST_BLOCK_SETUP_TICKS) :
|
|
LINKED_LIST_HEADER_READ_TICKS;
|
|
CPU::AddPendingTicks(setup_ticks);
|
|
remaining_ticks -= setup_ticks;
|
|
|
|
if (word_count > 0)
|
|
{
|
|
const TickCount block_ticks = TransferMemoryToDevice<channel>(transfer_addr + sizeof(header), 4, word_count);
|
|
CPU::AddPendingTicks(block_ticks);
|
|
remaining_ticks -= block_ticks;
|
|
}
|
|
|
|
current_address = next_address;
|
|
if (IsLinkedListTerminator(current_address))
|
|
{
|
|
// Terminator is 24 bits, so is MADR, so it'll always be 0xFFFFFF.
|
|
cs.base_address = LINKED_LIST_TERMINATOR;
|
|
CompleteTransfer(channel, cs);
|
|
return true;
|
|
}
|
|
}
|
|
|
|
cs.base_address = current_address;
|
|
if (cs.request)
|
|
{
|
|
// don't actually delay the transfer for the buffered ticks, this variable is dual-purposed.
|
|
s_halt_ticks_remaining = std::max(s_halt_ticks_remaining, 0);
|
|
|
|
// stall the transfer for a bit if we ran for too long
|
|
HaltTransfer(s_halt_ticks);
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
// linked list not yet complete
|
|
return true;
|
|
}
|
|
}
|
|
|
|
case SyncMode::Request:
|
|
{
|
|
Log_DebugFmt("DMA[{}]: Copying {} blocks of size {} ({} total words) {} 0x{:08X}", channel,
|
|
cs.block_control.request.GetBlockCount(), cs.block_control.request.GetBlockSize(),
|
|
cs.block_control.request.GetBlockCount() * cs.block_control.request.GetBlockSize(),
|
|
copy_to_device ? "from" : "to", current_address);
|
|
|
|
const u32 block_size = cs.block_control.request.GetBlockSize();
|
|
u32 blocks_remaining = cs.block_control.request.GetBlockCount();
|
|
TickCount ticks_remaining = s_max_slice_ticks;
|
|
|
|
if (copy_to_device)
|
|
{
|
|
do
|
|
{
|
|
const PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
|
|
if (CheckForBusError(channel, cs, transfer_addr, block_size * increment)) [[unlikely]]
|
|
{
|
|
cs.base_address = current_address;
|
|
cs.block_control.request.block_count = blocks_remaining;
|
|
return true;
|
|
}
|
|
|
|
const TickCount ticks = TransferMemoryToDevice<channel>(transfer_addr, increment, block_size);
|
|
CPU::AddPendingTicks(ticks);
|
|
|
|
ticks_remaining -= ticks;
|
|
blocks_remaining--;
|
|
|
|
current_address = (transfer_addr + (increment * block_size));
|
|
} while (cs.request && blocks_remaining > 0 && ticks_remaining > 0);
|
|
}
|
|
else
|
|
{
|
|
do
|
|
{
|
|
const PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
|
|
if (CheckForBusError(channel, cs, transfer_addr, block_size * increment)) [[unlikely]]
|
|
{
|
|
cs.base_address = current_address;
|
|
cs.block_control.request.block_count = blocks_remaining;
|
|
return true;
|
|
}
|
|
|
|
const TickCount ticks = TransferDeviceToMemory<channel>(transfer_addr, increment, block_size);
|
|
CPU::AddPendingTicks(ticks);
|
|
|
|
ticks_remaining -= ticks;
|
|
blocks_remaining--;
|
|
|
|
current_address = (transfer_addr + (increment * block_size));
|
|
} while (cs.request && blocks_remaining > 0 && ticks_remaining > 0);
|
|
}
|
|
|
|
cs.base_address = current_address;
|
|
cs.block_control.request.block_count = blocks_remaining;
|
|
|
|
// finish transfer later if the request was cleared
|
|
if (blocks_remaining > 0)
|
|
{
|
|
if (cs.request)
|
|
{
|
|
// we got halted
|
|
if (!s_unhalt_event->IsActive())
|
|
HaltTransfer(s_halt_ticks);
|
|
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
CompleteTransfer(channel, cs);
|
|
return true;
|
|
}
|
|
|
|
default:
|
|
Panic("Unimplemented sync mode");
|
|
}
|
|
|
|
UnreachableCode();
|
|
}
|
|
|
|
void DMA::HaltTransfer(TickCount duration)
|
|
{
|
|
s_halt_ticks_remaining += duration;
|
|
Log_DebugPrintf("Halting DMA for %d ticks", s_halt_ticks_remaining);
|
|
if (s_unhalt_event->IsActive())
|
|
return;
|
|
|
|
DebugAssert(!s_unhalt_event->IsActive());
|
|
s_unhalt_event->SetIntervalAndSchedule(s_halt_ticks_remaining);
|
|
}
|
|
|
|
void DMA::UnhaltTransfer(void*, TickCount ticks, TickCount ticks_late)
|
|
{
|
|
Log_DebugPrintf("Resuming DMA after %d ticks, %d ticks late", ticks, -(s_halt_ticks_remaining - ticks));
|
|
s_halt_ticks_remaining -= ticks;
|
|
s_unhalt_event->Deactivate();
|
|
|
|
// TODO: Use channel priority. But doing it in ascending order is probably good enough.
|
|
// Main thing is that OTC happens after GPU, because otherwise it'll wipe out the LL.
|
|
for (u32 i = 0; i < NUM_CHANNELS; i++)
|
|
{
|
|
if (CanTransferChannel(static_cast<Channel>(i), false))
|
|
{
|
|
if (!s_channel_transfer_functions[i]())
|
|
return;
|
|
}
|
|
}
|
|
|
|
// We didn't run too long, so reset timer.
|
|
s_halt_ticks_remaining = 0;
|
|
}
|
|
|
|
template<DMA::Channel channel>
|
|
TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count)
|
|
{
|
|
const u32 mask = Bus::g_ram_mask;
|
|
#ifdef _DEBUG
|
|
if ((address & mask) != address)
|
|
Log_DebugFmt("DMA TO {} from masked RAM address 0x{:08X} => 0x{:08X}", channel, address, (address & mask));
|
|
#endif
|
|
|
|
address &= mask;
|
|
|
|
const u32* src_pointer = reinterpret_cast<u32*>(Bus::g_ram + address);
|
|
if constexpr (channel != Channel::GPU)
|
|
{
|
|
if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address) [[unlikely]]
|
|
{
|
|
// Use temp buffer if it's wrapping around
|
|
if (s_transfer_buffer.size() < word_count)
|
|
s_transfer_buffer.resize(word_count);
|
|
src_pointer = s_transfer_buffer.data();
|
|
|
|
u8* ram_pointer = Bus::g_ram;
|
|
for (u32 i = 0; i < word_count; i++)
|
|
{
|
|
std::memcpy(&s_transfer_buffer[i], &ram_pointer[address], sizeof(u32));
|
|
address = (address + increment) & mask;
|
|
}
|
|
}
|
|
}
|
|
|
|
switch (channel)
|
|
{
|
|
case Channel::GPU:
|
|
{
|
|
if (g_gpu->BeginDMAWrite()) [[likely]]
|
|
{
|
|
u8* ram_pointer = Bus::g_ram;
|
|
for (u32 i = 0; i < word_count; i++)
|
|
{
|
|
u32 value;
|
|
std::memcpy(&value, &ram_pointer[address], sizeof(u32));
|
|
g_gpu->DMAWrite(address, value);
|
|
address = (address + increment) & mask;
|
|
}
|
|
g_gpu->EndDMAWrite();
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Channel::SPU:
|
|
SPU::DMAWrite(src_pointer, word_count);
|
|
break;
|
|
|
|
case Channel::MDECin:
|
|
MDEC::DMAWrite(src_pointer, word_count);
|
|
break;
|
|
|
|
case Channel::CDROM:
|
|
case Channel::MDECout:
|
|
case Channel::PIO:
|
|
default:
|
|
Log_ErrorPrintf("Unhandled DMA channel %u for device write", static_cast<u32>(channel));
|
|
break;
|
|
}
|
|
|
|
return Bus::GetDMARAMTickCount(word_count);
|
|
}
|
|
|
|
template<DMA::Channel channel>
|
|
TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count)
|
|
{
|
|
const u32 mask = Bus::g_ram_mask;
|
|
#ifdef _DEBUG
|
|
if ((address & mask) != address)
|
|
Log_DebugFmt("DMA FROM {} to masked RAM address 0x{:08X} => 0x{:08X}", channel, address, (address & mask));
|
|
#endif
|
|
|
|
// TODO: This might not be correct for OTC.
|
|
address &= mask;
|
|
|
|
if constexpr (channel == Channel::OTC)
|
|
{
|
|
// clear ordering table
|
|
u8* ram_pointer = Bus::g_ram;
|
|
const u32 word_count_less_1 = word_count - 1;
|
|
for (u32 i = 0; i < word_count_less_1; i++)
|
|
{
|
|
u32 next = ((address - 4) & mask);
|
|
std::memcpy(&ram_pointer[address], &next, sizeof(next));
|
|
address = next;
|
|
}
|
|
|
|
const u32 terminator = UINT32_C(0xFFFFFF);
|
|
std::memcpy(&ram_pointer[address], &terminator, sizeof(terminator));
|
|
return Bus::GetDMARAMTickCount(word_count);
|
|
}
|
|
|
|
u32* dest_pointer = reinterpret_cast<u32*>(&Bus::g_ram[address]);
|
|
if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address) [[unlikely]]
|
|
{
|
|
// Use temp buffer if it's wrapping around
|
|
if (s_transfer_buffer.size() < word_count)
|
|
s_transfer_buffer.resize(word_count);
|
|
dest_pointer = s_transfer_buffer.data();
|
|
}
|
|
|
|
// Read from device.
|
|
switch (channel)
|
|
{
|
|
case Channel::GPU:
|
|
g_gpu->DMARead(dest_pointer, word_count);
|
|
break;
|
|
|
|
case Channel::CDROM:
|
|
CDROM::DMARead(dest_pointer, word_count);
|
|
break;
|
|
|
|
case Channel::SPU:
|
|
SPU::DMARead(dest_pointer, word_count);
|
|
break;
|
|
|
|
case Channel::MDECout:
|
|
MDEC::DMARead(dest_pointer, word_count);
|
|
break;
|
|
|
|
default:
|
|
Log_ErrorPrintf("Unhandled DMA channel %u for device read", static_cast<u32>(channel));
|
|
std::fill_n(dest_pointer, word_count, UINT32_C(0xFFFFFFFF));
|
|
break;
|
|
}
|
|
|
|
if (dest_pointer == s_transfer_buffer.data()) [[unlikely]]
|
|
{
|
|
u8* ram_pointer = Bus::g_ram;
|
|
for (u32 i = 0; i < word_count; i++)
|
|
{
|
|
std::memcpy(&ram_pointer[address], &s_transfer_buffer[i], sizeof(u32));
|
|
address = (address + increment) & mask;
|
|
}
|
|
}
|
|
|
|
return Bus::GetDMARAMTickCount(word_count);
|
|
}
|
|
|
|
void DMA::DrawDebugStateWindow()
|
|
{
|
|
static constexpr u32 NUM_COLUMNS = 10;
|
|
static constexpr std::array<const char*, NUM_COLUMNS> column_names = {
|
|
{"#", "Req", "Direction", "Chopping", "Mode", "Busy", "Enable", "Priority", "IRQ", "Flag"}};
|
|
static constexpr std::array<const char*, 4> sync_mode_names = {{"Manual", "Request", "LinkedList", "Reserved"}};
|
|
|
|
const float framebuffer_scale = Host::GetOSDScale();
|
|
|
|
ImGui::SetNextWindowSize(ImVec2(850.0f * framebuffer_scale, 250.0f * framebuffer_scale), ImGuiCond_FirstUseEver);
|
|
if (!ImGui::Begin("DMA State", nullptr))
|
|
{
|
|
ImGui::End();
|
|
return;
|
|
}
|
|
|
|
ImGui::Columns(NUM_COLUMNS);
|
|
ImGui::SetColumnWidth(0, 100.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(1, 50.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(2, 100.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(3, 150.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(4, 80.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(5, 80.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(6, 80.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(7, 80.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(8, 80.0f * framebuffer_scale);
|
|
ImGui::SetColumnWidth(9, 80.0f * framebuffer_scale);
|
|
|
|
for (const char* title : column_names)
|
|
{
|
|
ImGui::TextUnformatted(title);
|
|
ImGui::NextColumn();
|
|
}
|
|
|
|
const ImVec4 active(1.0f, 1.0f, 1.0f, 1.0f);
|
|
const ImVec4 inactive(0.5f, 0.5f, 0.5f, 1.0f);
|
|
|
|
for (u32 i = 0; i < NUM_CHANNELS; i++)
|
|
{
|
|
const ChannelState& cs = s_state[i];
|
|
|
|
ImGui::TextColored(cs.channel_control.enable_busy ? active : inactive, "%u[%s]", i, s_channel_names[i]);
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(cs.request ? active : inactive, cs.request ? "Yes" : "No");
|
|
ImGui::NextColumn();
|
|
ImGui::Text("%s%s", cs.channel_control.copy_to_device ? "FromRAM" : "ToRAM",
|
|
cs.channel_control.address_step_reverse ? " Addr+" : " Addr-");
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(cs.channel_control.chopping_enable ? active : inactive, "%s/%u/%u",
|
|
cs.channel_control.chopping_enable ? "Yes" : "No",
|
|
cs.channel_control.chopping_cpu_window_size.GetValue(),
|
|
cs.channel_control.chopping_dma_window_size.GetValue());
|
|
ImGui::NextColumn();
|
|
ImGui::Text("%s", sync_mode_names[static_cast<u8>(cs.channel_control.sync_mode.GetValue())]);
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(cs.channel_control.enable_busy ? active : inactive, "%s%s",
|
|
cs.channel_control.enable_busy ? "Busy" : "Idle",
|
|
cs.channel_control.start_trigger ? " (Trigger)" : "");
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive,
|
|
s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive, "%u",
|
|
s_DPCR.GetPriority(static_cast<Channel>(i)));
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(s_DICR.GetIRQEnabled(static_cast<Channel>(i)) ? active : inactive,
|
|
s_DICR.GetIRQEnabled(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
|
ImGui::NextColumn();
|
|
ImGui::TextColored(s_DICR.GetIRQFlag(static_cast<Channel>(i)) ? active : inactive,
|
|
s_DICR.GetIRQFlag(static_cast<Channel>(i)) ? "IRQ" : "");
|
|
ImGui::NextColumn();
|
|
}
|
|
|
|
ImGui::Columns(1);
|
|
ImGui::End();
|
|
}
|
|
|
|
// Instantiate channel functions.
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::MDECin>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::MDECin>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::MDECin>();
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::MDECout>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::MDECout>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::MDECout>();
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::GPU>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::GPU>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::GPU>();
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::CDROM>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::CDROM>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::CDROM>();
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::SPU>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::SPU>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::SPU>();
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::PIO>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::PIO>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::PIO>();
|
|
template TickCount DMA::TransferDeviceToMemory<DMA::Channel::OTC>(u32 address, u32 increment, u32 word_count);
|
|
template TickCount DMA::TransferMemoryToDevice<DMA::Channel::OTC>(u32 address, u32 increment, u32 word_count);
|
|
template bool DMA::TransferChannel<DMA::Channel::OTC>();
|