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https://github.com/stenzek/duckstation.git
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ac1bb905fe
Tenga Seiha does a bunch of completely-invalid VRAM writes on boot, then expects GPU idle to be set. It's unclear what actually happens, I need to write another test, but for now, just skip these uploads. Not setting GPU idle during the write command breaks Doom, so that's not an option.
636 lines
20 KiB
C++
636 lines
20 KiB
C++
// SPDX-FileCopyrightText: 2019-2022 Connor McLaughlin <stenzek@gmail.com>
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// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
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#include "common/assert.h"
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#include "common/log.h"
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#include "common/string_util.h"
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#include "gpu.h"
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#include "interrupt_controller.h"
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#include "system.h"
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#include "texture_replacements.h"
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Log_SetChannel(GPU);
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#define CHECK_COMMAND_SIZE(num_words) \
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if (m_fifo.GetSize() < num_words) \
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{ \
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m_command_total_words = num_words; \
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return false; \
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}
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static u32 s_cpu_to_vram_dump_id = 1;
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static u32 s_vram_to_cpu_dump_id = 1;
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static constexpr u32 ReplaceZero(u32 value, u32 value_for_zero)
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{
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return value == 0 ? value_for_zero : value;
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}
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void GPU::TryExecuteCommands()
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{
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while (m_pending_command_ticks <= m_max_run_ahead && !m_fifo.IsEmpty())
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{
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switch (m_blitter_state)
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{
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case BlitterState::Idle:
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{
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const u32 command = FifoPeek(0) >> 24;
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if ((this->*s_GP0_command_handler_table[command])())
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continue;
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else
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return;
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}
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case BlitterState::WritingVRAM:
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{
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DebugAssert(m_blit_remaining_words > 0);
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const u32 words_to_copy = std::min(m_blit_remaining_words, m_fifo.GetSize());
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m_blit_buffer.reserve(m_blit_buffer.size() + words_to_copy);
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for (u32 i = 0; i < words_to_copy; i++)
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m_blit_buffer.push_back(FifoPop());
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m_blit_remaining_words -= words_to_copy;
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DEBUG_LOG("VRAM write burst of {} words, {} words remaining", words_to_copy, m_blit_remaining_words);
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if (m_blit_remaining_words == 0)
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FinishVRAMWrite();
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continue;
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}
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case BlitterState::ReadingVRAM:
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{
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return;
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}
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break;
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case BlitterState::DrawingPolyLine:
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{
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const u32 words_per_vertex = m_render_command.shading_enable ? 2 : 1;
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u32 terminator_index =
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m_render_command.shading_enable ? ((static_cast<u32>(m_blit_buffer.size()) & 1u) ^ 1u) : 0u;
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for (; terminator_index < m_fifo.GetSize(); terminator_index += words_per_vertex)
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{
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// polyline must have at least two vertices, and the terminator is (word & 0xf000f000) == 0x50005000.
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// terminator is on the first word for the vertex
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if ((FifoPeek(terminator_index) & UINT32_C(0xF000F000)) == UINT32_C(0x50005000))
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break;
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}
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const bool found_terminator = (terminator_index < m_fifo.GetSize());
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const u32 words_to_copy = std::min(terminator_index, m_fifo.GetSize());
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if (words_to_copy > 0)
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{
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m_blit_buffer.reserve(m_blit_buffer.size() + words_to_copy);
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for (u32 i = 0; i < words_to_copy; i++)
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m_blit_buffer.push_back(FifoPop());
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}
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DEBUG_LOG("Added {} words to polyline", words_to_copy);
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if (found_terminator)
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{
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// drop terminator
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m_fifo.RemoveOne();
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DEBUG_LOG("Drawing poly-line with {} vertices", GetPolyLineVertexCount());
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DispatchRenderCommand();
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m_blit_buffer.clear();
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EndCommand();
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continue;
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}
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}
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break;
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}
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}
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}
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void GPU::ExecuteCommands()
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{
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const bool was_executing_from_event = std::exchange(m_executing_commands, true);
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TryExecuteCommands();
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UpdateDMARequest();
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UpdateGPUIdle();
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m_executing_commands = was_executing_from_event;
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if (!was_executing_from_event)
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UpdateCommandTickEvent();
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}
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void GPU::EndCommand()
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{
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m_blitter_state = BlitterState::Idle;
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m_command_total_words = 0;
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}
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GPU::GP0CommandHandlerTable GPU::GenerateGP0CommandHandlerTable()
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{
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GP0CommandHandlerTable table = {};
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for (u32 i = 0; i < static_cast<u32>(table.size()); i++)
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table[i] = &GPU::HandleUnknownGP0Command;
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table[0x00] = &GPU::HandleNOPCommand;
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table[0x01] = &GPU::HandleClearCacheCommand;
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table[0x02] = &GPU::HandleFillRectangleCommand;
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table[0x03] = &GPU::HandleNOPCommand;
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for (u32 i = 0x04; i <= 0x1E; i++)
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table[i] = &GPU::HandleNOPCommand;
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table[0x1F] = &GPU::HandleInterruptRequestCommand;
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for (u32 i = 0x20; i <= 0x7F; i++)
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{
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const GPURenderCommand rc{i << 24};
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switch (rc.primitive)
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{
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case GPUPrimitive::Polygon:
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table[i] = &GPU::HandleRenderPolygonCommand;
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break;
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case GPUPrimitive::Line:
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table[i] = rc.polyline ? &GPU::HandleRenderPolyLineCommand : &GPU::HandleRenderLineCommand;
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break;
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case GPUPrimitive::Rectangle:
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table[i] = &GPU::HandleRenderRectangleCommand;
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break;
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default:
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table[i] = &GPU::HandleUnknownGP0Command;
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break;
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}
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}
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table[0xE0] = &GPU::HandleNOPCommand;
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table[0xE1] = &GPU::HandleSetDrawModeCommand;
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table[0xE2] = &GPU::HandleSetTextureWindowCommand;
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table[0xE3] = &GPU::HandleSetDrawingAreaTopLeftCommand;
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table[0xE4] = &GPU::HandleSetDrawingAreaBottomRightCommand;
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table[0xE5] = &GPU::HandleSetDrawingOffsetCommand;
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table[0xE6] = &GPU::HandleSetMaskBitCommand;
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for (u32 i = 0xE7; i <= 0xEF; i++)
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table[i] = &GPU::HandleNOPCommand;
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for (u32 i = 0x80; i <= 0x9F; i++)
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table[i] = &GPU::HandleCopyRectangleVRAMToVRAMCommand;
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for (u32 i = 0xA0; i <= 0xBF; i++)
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table[i] = &GPU::HandleCopyRectangleCPUToVRAMCommand;
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for (u32 i = 0xC0; i <= 0xDF; i++)
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table[i] = &GPU::HandleCopyRectangleVRAMToCPUCommand;
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table[0xFF] = &GPU::HandleNOPCommand;
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return table;
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}
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bool GPU::HandleUnknownGP0Command()
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{
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const u32 command = FifoPeek() >> 24;
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ERROR_LOG("Unimplemented GP0 command 0x{:02X}", command);
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SmallString dump;
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for (u32 i = 0; i < m_fifo.GetSize(); i++)
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dump.append_format("{}{:08X}", (i > 0) ? " " : "", FifoPeek(i));
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ERROR_LOG("FIFO: {}", dump);
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m_fifo.RemoveOne();
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EndCommand();
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return true;
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}
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bool GPU::HandleNOPCommand()
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{
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m_fifo.RemoveOne();
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EndCommand();
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return true;
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}
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bool GPU::HandleClearCacheCommand()
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{
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DEBUG_LOG("GP0 clear cache");
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m_draw_mode.SetTexturePageChanged();
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InvalidateCLUT();
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m_fifo.RemoveOne();
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleInterruptRequestCommand()
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{
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DEBUG_LOG("GP0 interrupt request");
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m_GPUSTAT.interrupt_request = true;
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InterruptController::SetLineState(InterruptController::IRQ::GPU, true);
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m_fifo.RemoveOne();
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleSetDrawModeCommand()
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{
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const u32 param = FifoPop() & 0x00FFFFFFu;
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DEBUG_LOG("Set draw mode {:08X}", param);
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SetDrawMode(Truncate16(param));
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleSetTextureWindowCommand()
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{
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const u32 param = FifoPop() & 0x00FFFFFFu;
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SetTextureWindow(param);
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleSetDrawingAreaTopLeftCommand()
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{
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const u32 param = FifoPop() & 0x00FFFFFFu;
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const u32 left = param & DRAWING_AREA_COORD_MASK;
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const u32 top = (param >> 10) & DRAWING_AREA_COORD_MASK;
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DEBUG_LOG("Set drawing area top-left: ({}, {})", left, top);
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if (m_drawing_area.left != left || m_drawing_area.top != top)
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{
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FlushRender();
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m_drawing_area.left = left;
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m_drawing_area.top = top;
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m_drawing_area_changed = true;
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}
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleSetDrawingAreaBottomRightCommand()
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{
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const u32 param = FifoPop() & 0x00FFFFFFu;
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const u32 right = param & DRAWING_AREA_COORD_MASK;
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const u32 bottom = (param >> 10) & DRAWING_AREA_COORD_MASK;
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DEBUG_LOG("Set drawing area bottom-right: ({}, {})", m_drawing_area.right, m_drawing_area.bottom);
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if (m_drawing_area.right != right || m_drawing_area.bottom != bottom)
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{
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FlushRender();
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m_drawing_area.right = right;
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m_drawing_area.bottom = bottom;
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m_drawing_area_changed = true;
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}
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleSetDrawingOffsetCommand()
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{
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const u32 param = FifoPop() & 0x00FFFFFFu;
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const s32 x = SignExtendN<11, s32>(param & 0x7FFu);
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const s32 y = SignExtendN<11, s32>((param >> 11) & 0x7FFu);
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DEBUG_LOG("Set drawing offset ({}, {})", m_drawing_offset.x, m_drawing_offset.y);
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if (m_drawing_offset.x != x || m_drawing_offset.y != y)
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{
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FlushRender();
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m_drawing_offset.x = x;
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m_drawing_offset.y = y;
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}
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleSetMaskBitCommand()
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{
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const u32 param = FifoPop() & 0x00FFFFFFu;
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constexpr u32 gpustat_mask = (1 << 11) | (1 << 12);
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const u32 gpustat_bits = (param & 0x03) << 11;
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if ((m_GPUSTAT.bits & gpustat_mask) != gpustat_bits)
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{
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FlushRender();
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m_GPUSTAT.bits = (m_GPUSTAT.bits & ~gpustat_mask) | gpustat_bits;
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}
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DEBUG_LOG("Set mask bit {} {}", BoolToUInt32(m_GPUSTAT.set_mask_while_drawing),
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BoolToUInt32(m_GPUSTAT.check_mask_before_draw));
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AddCommandTicks(1);
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EndCommand();
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return true;
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}
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bool GPU::HandleRenderPolygonCommand()
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{
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const GPURenderCommand rc{FifoPeek(0)};
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// shaded vertices use the colour from the first word for the first vertex
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const u32 words_per_vertex = 1 + BoolToUInt32(rc.texture_enable) + BoolToUInt32(rc.shading_enable);
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const u32 num_vertices = rc.quad_polygon ? 4 : 3;
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const u32 total_words = words_per_vertex * num_vertices + BoolToUInt32(!rc.shading_enable);
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CHECK_COMMAND_SIZE(total_words);
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if (IsInterlacedRenderingEnabled() && IsCRTCScanlinePending())
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SynchronizeCRTC();
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// setup time
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static constexpr u16 s_setup_time[2][2][2] = {{{46, 226}, {334, 496}}, {{82, 262}, {370, 532}}};
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const TickCount setup_ticks = static_cast<TickCount>(ZeroExtend32(
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s_setup_time[BoolToUInt8(rc.quad_polygon)][BoolToUInt8(rc.shading_enable)][BoolToUInt8(rc.texture_enable)]));
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AddCommandTicks(setup_ticks);
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TRACE_LOG("Render {} {} {} {} polygon ({} verts, {} words per vert), {} setup ticks",
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rc.quad_polygon ? "four-point" : "three-point", rc.transparency_enable ? "semi-transparent" : "opaque",
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rc.texture_enable ? "textured" : "non-textured", rc.shading_enable ? "shaded" : "monochrome", num_vertices,
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words_per_vertex, setup_ticks);
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// set draw state up
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if (rc.texture_enable)
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{
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const u16 texpage_attribute = Truncate16((rc.shading_enable ? FifoPeek(5) : FifoPeek(4)) >> 16);
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SetDrawMode((texpage_attribute & GPUDrawModeReg::POLYGON_TEXPAGE_MASK) |
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(m_draw_mode.mode_reg.bits & ~GPUDrawModeReg::POLYGON_TEXPAGE_MASK));
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SetTexturePalette(Truncate16(FifoPeek(2) >> 16));
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UpdateCLUTIfNeeded(m_draw_mode.mode_reg.texture_mode, m_draw_mode.palette_reg);
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}
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m_counters.num_vertices += num_vertices;
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m_counters.num_primitives++;
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m_render_command.bits = rc.bits;
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m_fifo.RemoveOne();
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DispatchRenderCommand();
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EndCommand();
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return true;
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}
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bool GPU::HandleRenderRectangleCommand()
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{
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const GPURenderCommand rc{FifoPeek(0)};
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const u32 total_words =
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2 + BoolToUInt32(rc.texture_enable) + BoolToUInt32(rc.rectangle_size == GPUDrawRectangleSize::Variable);
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CHECK_COMMAND_SIZE(total_words);
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if (IsInterlacedRenderingEnabled() && IsCRTCScanlinePending())
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SynchronizeCRTC();
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if (rc.texture_enable)
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{
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SetTexturePalette(Truncate16(FifoPeek(2) >> 16));
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UpdateCLUTIfNeeded(m_draw_mode.mode_reg.texture_mode, m_draw_mode.palette_reg);
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}
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const TickCount setup_ticks = 16;
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AddCommandTicks(setup_ticks);
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TRACE_LOG("Render {} {} {} rectangle ({} words), {} setup ticks",
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rc.transparency_enable ? "semi-transparent" : "opaque", rc.texture_enable ? "textured" : "non-textured",
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rc.shading_enable ? "shaded" : "monochrome", total_words, setup_ticks);
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m_counters.num_vertices++;
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m_counters.num_primitives++;
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m_render_command.bits = rc.bits;
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m_fifo.RemoveOne();
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DispatchRenderCommand();
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EndCommand();
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return true;
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}
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bool GPU::HandleRenderLineCommand()
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{
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const GPURenderCommand rc{FifoPeek(0)};
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const u32 total_words = rc.shading_enable ? 4 : 3;
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CHECK_COMMAND_SIZE(total_words);
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if (IsInterlacedRenderingEnabled() && IsCRTCScanlinePending())
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SynchronizeCRTC();
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TRACE_LOG("Render {} {} line ({} total words)", rc.transparency_enable ? "semi-transparent" : "opaque",
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rc.shading_enable ? "shaded" : "monochrome", total_words);
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m_counters.num_vertices += 2;
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m_counters.num_primitives++;
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m_render_command.bits = rc.bits;
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m_fifo.RemoveOne();
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DispatchRenderCommand();
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EndCommand();
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return true;
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}
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bool GPU::HandleRenderPolyLineCommand()
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{
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// always read the first two vertices, we test for the terminator after that
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const GPURenderCommand rc{FifoPeek(0)};
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const u32 min_words = rc.shading_enable ? 3 : 4;
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CHECK_COMMAND_SIZE(min_words);
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if (IsInterlacedRenderingEnabled() && IsCRTCScanlinePending())
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SynchronizeCRTC();
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const TickCount setup_ticks = 16;
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AddCommandTicks(setup_ticks);
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TRACE_LOG("Render {} {} poly-line, {} setup ticks", rc.transparency_enable ? "semi-transparent" : "opaque",
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rc.shading_enable ? "shaded" : "monochrome", setup_ticks);
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m_render_command.bits = rc.bits;
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m_fifo.RemoveOne();
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const u32 words_to_pop = min_words - 1;
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// m_blit_buffer.resize(words_to_pop);
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// FifoPopRange(m_blit_buffer.data(), words_to_pop);
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m_blit_buffer.reserve(words_to_pop);
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for (u32 i = 0; i < words_to_pop; i++)
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m_blit_buffer.push_back(Truncate32(FifoPop()));
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// polyline goes via a different path through the blit buffer
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m_blitter_state = BlitterState::DrawingPolyLine;
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m_command_total_words = 0;
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return true;
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}
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bool GPU::HandleFillRectangleCommand()
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{
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CHECK_COMMAND_SIZE(3);
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if (IsInterlacedRenderingEnabled() && IsCRTCScanlinePending())
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SynchronizeCRTC();
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FlushRender();
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const u32 color = FifoPop() & 0x00FFFFFF;
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const u32 dst_x = FifoPeek() & 0x3F0;
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const u32 dst_y = (FifoPop() >> 16) & VRAM_HEIGHT_MASK;
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const u32 width = ((FifoPeek() & VRAM_WIDTH_MASK) + 0xF) & ~0xF;
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const u32 height = (FifoPop() >> 16) & VRAM_HEIGHT_MASK;
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DEBUG_LOG("Fill VRAM rectangle offset=({},{}), size=({},{})", dst_x, dst_y, width, height);
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if (width > 0 && height > 0)
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FillVRAM(dst_x, dst_y, width, height, color);
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m_counters.num_writes++;
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AddCommandTicks(46 + ((width / 8) + 9) * height);
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EndCommand();
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return true;
|
|
}
|
|
|
|
bool GPU::HandleCopyRectangleCPUToVRAMCommand()
|
|
{
|
|
CHECK_COMMAND_SIZE(3);
|
|
m_fifo.RemoveOne();
|
|
|
|
const u32 coords = FifoPop();
|
|
const u32 size = FifoPop();
|
|
|
|
// Tenga Seiha does a bunch of completely-invalid VRAM writes on boot, then expects GPU idle to be set.
|
|
// It's unclear what actually happens, I need to write another test, but for now, just skip these uploads.
|
|
// Not setting GPU idle during the write command breaks Doom, so that's not an option.
|
|
if (size == 0xFFFFFFFFu) [[unlikely]]
|
|
{
|
|
ERROR_LOG("Ignoring likely-invalid VRAM write to ({},{})", (coords & VRAM_WIDTH_MASK),
|
|
((coords >> 16) & VRAM_HEIGHT_MASK));
|
|
return true;
|
|
}
|
|
|
|
const u32 dst_x = coords & VRAM_WIDTH_MASK;
|
|
const u32 dst_y = (coords >> 16) & VRAM_HEIGHT_MASK;
|
|
const u32 copy_width = ReplaceZero(size & VRAM_WIDTH_MASK, 0x400);
|
|
const u32 copy_height = ReplaceZero((size >> 16) & VRAM_HEIGHT_MASK, 0x200);
|
|
const u32 num_pixels = copy_width * copy_height;
|
|
const u32 num_words = ((num_pixels + 1) / 2);
|
|
|
|
DEBUG_LOG("Copy rectangle from CPU to VRAM offset=({},{}), size=({},{})", dst_x, dst_y, copy_width, copy_height);
|
|
|
|
EndCommand();
|
|
|
|
m_blitter_state = BlitterState::WritingVRAM;
|
|
m_blit_buffer.reserve(num_words);
|
|
m_blit_remaining_words = num_words;
|
|
m_vram_transfer.x = Truncate16(dst_x);
|
|
m_vram_transfer.y = Truncate16(dst_y);
|
|
m_vram_transfer.width = Truncate16(copy_width);
|
|
m_vram_transfer.height = Truncate16(copy_height);
|
|
return true;
|
|
}
|
|
|
|
void GPU::FinishVRAMWrite()
|
|
{
|
|
if (IsInterlacedRenderingEnabled() && IsCRTCScanlinePending())
|
|
SynchronizeCRTC();
|
|
|
|
FlushRender();
|
|
|
|
if (m_blit_remaining_words == 0)
|
|
{
|
|
if (g_settings.debugging.dump_cpu_to_vram_copies)
|
|
{
|
|
DumpVRAMToFile(TinyString::from_format("cpu_to_vram_copy_{}.png", s_cpu_to_vram_dump_id++), m_vram_transfer.width,
|
|
m_vram_transfer.height, sizeof(u16) * m_vram_transfer.width, m_blit_buffer.data(), true);
|
|
}
|
|
|
|
if (g_settings.texture_replacements.ShouldDumpVRAMWrite(m_vram_transfer.width, m_vram_transfer.height))
|
|
{
|
|
g_texture_replacements.DumpVRAMWrite(m_vram_transfer.width, m_vram_transfer.height,
|
|
reinterpret_cast<const u16*>(m_blit_buffer.data()));
|
|
}
|
|
|
|
UpdateVRAM(m_vram_transfer.x, m_vram_transfer.y, m_vram_transfer.width, m_vram_transfer.height,
|
|
m_blit_buffer.data(), m_GPUSTAT.set_mask_while_drawing, m_GPUSTAT.check_mask_before_draw);
|
|
}
|
|
else
|
|
{
|
|
const u32 num_pixels = ZeroExtend32(m_vram_transfer.width) * ZeroExtend32(m_vram_transfer.height);
|
|
const u32 num_words = (num_pixels + 1) / 2;
|
|
const u32 transferred_words = num_words - m_blit_remaining_words;
|
|
const u32 transferred_pixels = transferred_words * 2;
|
|
const u32 transferred_full_rows = transferred_pixels / m_vram_transfer.width;
|
|
const u32 transferred_width_last_row = transferred_pixels % m_vram_transfer.width;
|
|
|
|
WARNING_LOG("Partial VRAM write - transfer finished with {} of {} words remaining ({} full rows, {} last row)",
|
|
m_blit_remaining_words, num_words, transferred_full_rows, transferred_width_last_row);
|
|
|
|
const u8* blit_ptr = reinterpret_cast<const u8*>(m_blit_buffer.data());
|
|
if (transferred_full_rows > 0)
|
|
{
|
|
UpdateVRAM(m_vram_transfer.x, m_vram_transfer.y, m_vram_transfer.width, transferred_full_rows, blit_ptr,
|
|
m_GPUSTAT.set_mask_while_drawing, m_GPUSTAT.check_mask_before_draw);
|
|
blit_ptr += (ZeroExtend32(m_vram_transfer.width) * transferred_full_rows) * sizeof(u16);
|
|
}
|
|
if (transferred_width_last_row > 0)
|
|
{
|
|
UpdateVRAM(m_vram_transfer.x, m_vram_transfer.y + transferred_full_rows, transferred_width_last_row, 1, blit_ptr,
|
|
m_GPUSTAT.set_mask_while_drawing, m_GPUSTAT.check_mask_before_draw);
|
|
}
|
|
}
|
|
|
|
m_counters.num_writes++;
|
|
m_blit_buffer.clear();
|
|
m_vram_transfer = {};
|
|
m_blitter_state = BlitterState::Idle;
|
|
}
|
|
|
|
bool GPU::HandleCopyRectangleVRAMToCPUCommand()
|
|
{
|
|
CHECK_COMMAND_SIZE(3);
|
|
m_fifo.RemoveOne();
|
|
|
|
m_vram_transfer.x = Truncate16(FifoPeek() & VRAM_WIDTH_MASK);
|
|
m_vram_transfer.y = Truncate16((FifoPop() >> 16) & VRAM_HEIGHT_MASK);
|
|
m_vram_transfer.width = ((Truncate16(FifoPeek()) - 1) & VRAM_WIDTH_MASK) + 1;
|
|
m_vram_transfer.height = ((Truncate16(FifoPop() >> 16) - 1) & VRAM_HEIGHT_MASK) + 1;
|
|
|
|
DEBUG_LOG("Copy rectangle from VRAM to CPU offset=({},{}), size=({},{})", m_vram_transfer.x, m_vram_transfer.y,
|
|
m_vram_transfer.width, m_vram_transfer.height);
|
|
DebugAssert(m_vram_transfer.col == 0 && m_vram_transfer.row == 0);
|
|
|
|
// all rendering should be done first...
|
|
FlushRender();
|
|
|
|
// ensure VRAM shadow is up to date
|
|
ReadVRAM(m_vram_transfer.x, m_vram_transfer.y, m_vram_transfer.width, m_vram_transfer.height);
|
|
|
|
if (g_settings.debugging.dump_vram_to_cpu_copies)
|
|
{
|
|
DumpVRAMToFile(TinyString::from_format("vram_to_cpu_copy_{}.png", s_vram_to_cpu_dump_id++), m_vram_transfer.width,
|
|
m_vram_transfer.height, sizeof(u16) * VRAM_WIDTH,
|
|
&g_vram[m_vram_transfer.y * VRAM_WIDTH + m_vram_transfer.x], true);
|
|
}
|
|
|
|
// switch to pixel-by-pixel read state
|
|
m_counters.num_reads++;
|
|
m_blitter_state = BlitterState::ReadingVRAM;
|
|
m_command_total_words = 0;
|
|
return true;
|
|
}
|
|
|
|
bool GPU::HandleCopyRectangleVRAMToVRAMCommand()
|
|
{
|
|
CHECK_COMMAND_SIZE(4);
|
|
m_fifo.RemoveOne();
|
|
|
|
const u32 src_x = FifoPeek() & VRAM_WIDTH_MASK;
|
|
const u32 src_y = (FifoPop() >> 16) & VRAM_HEIGHT_MASK;
|
|
const u32 dst_x = FifoPeek() & VRAM_WIDTH_MASK;
|
|
const u32 dst_y = (FifoPop() >> 16) & VRAM_HEIGHT_MASK;
|
|
const u32 width = ReplaceZero(FifoPeek() & VRAM_WIDTH_MASK, 0x400);
|
|
const u32 height = ReplaceZero((FifoPop() >> 16) & VRAM_HEIGHT_MASK, 0x200);
|
|
|
|
DEBUG_LOG("Copy rectangle from VRAM to VRAM src=({},{}), dst=({},{}), size=({},{})", src_x, src_y, dst_x, dst_y,
|
|
width, height);
|
|
|
|
// Some VRAM copies aren't going to do anything. Most games seem to send a 2x2 VRAM copy at the end of a frame.
|
|
const bool skip_copy =
|
|
width == 0 || height == 0 || (src_x == dst_x && src_y == dst_y && !m_GPUSTAT.set_mask_while_drawing);
|
|
if (!skip_copy)
|
|
{
|
|
m_counters.num_copies++;
|
|
|
|
FlushRender();
|
|
CopyVRAM(src_x, src_y, dst_x, dst_y, width, height);
|
|
}
|
|
|
|
AddCommandTicks(width * height * 2);
|
|
EndCommand();
|
|
return true;
|
|
}
|